1. Field of the Invention
The present invention generally relates to semiconductor devices, and particularly relates to a semiconductor device in which a plurality of transistor units are provided on a common substrate, an emitter ballast resistor is connected to the emitter of each transistor unit, and a stabilizing resistor is connected between the base and emitter of each transistor unit.
2. Description of the Prior Art
An example of a semiconductor device having multiple transistor units connected in parallel and formed in a common substrate is a semiconductor device having a structure generally called a mesh-or multi-emitter structure, as illustrated by an equivalent circuit in FIG. 1. A multi-emitter structure may include an emitter ballast resistor 8, for example, made of a polycrystalline silicon resistor connected between an emitter contact electrode 22 of each transistor unit 21 and a common emitter electrode 23 so as to expand the area of safe operation of each transistor unit. Additionally, a resistor 26 is connected between a common base electrode 25 and the common emitter electrode 23 for the sake of stabilization of the withstanding voltage between the collector and emitter of each transistor unit.
FIG. 2 is a sectional view of an example of such a semiconductor device. An N-type collector region 2, a P-type base region 3 and an N-type emitter region 4 are successively formed in a substrate 1, and then the substrate 1 is coated with an insulating film 5 of silicon dioxide, SiO.sub.2. Base electrodes 6 of the respective transistor units are formed so as to contact the base region 3 through the holes of the insulating film 5.
Base electrodes 6 of the respective transistor units are connected in parallel to each other, and a base terminal B is led out from a bonding portion (not shown) of the connection. In FIG. 2, the parallel connection of the respective base electrodes 6 is shown by lines in the form of an equivalent circuit.
Emitter contact electrodes 7 of the respective transistor units are formed so as to contact with emitter region 4 through the holes of the insulting film 5. Emitter ballast resistors 8 of polycrystalline silicon film are formed on insulating film 5 so as to contact with the respective emitter contact electrodes 7.
Moreover, emitter electrodes 9 are provided on the insulating film 5 so as to connect with the respective emitter ballast resistor 8. Emitter electrodes 9 of the respective transistor units are connected in parallel to each other, and an emitter terminal E is led out from the bonding portion (not shown) of the connection. In FIG. 2 the parallel connection of the respective emitter electrodes 9 is shown by lines in the form of an equivalent circuit.
In base region 3, an elongated N-type region 41 of the same conductivity type as emitter region 4 is formed in the surface layer of base region 3, and insulating film 5 is removed to expose both ends 11 and 12 of region 41 so as to make contact with one base electrode 6 and one emitter electrode 9, respectively. Thus, the region 41 acts as a resistive region between base electrode 6 and emitter electrode 9, so that it is possible to ensure the stabilization of the withstanding voltage between the collector and the emitter of each transistor.
However, owing to the provision of the N-type resistive region 41, an NPN transistor structure is formed by the region 41, and the respective portions of base region 3 and collector region 2, which are located just under region 41. These parasitic transistor effects are weak in the region near end 11 contacting with base electrode 6 since an emitter current flows into the emitter through resistive region 41. The parasitic transistor effects are strong near end 12 of region 41 contacting emitter electrode 9 since this region acts as an emitter. Therefore, there has been a problem in that the transistor formed in the region near end 12 is not protected by the emitter ballast resistor so that the area of safe operation of the transistor becomes smallest and the device breaks down in this portion, making it impossible to obtain a desired area of safe operation for the semiconductor device.